1. Field of the Invention
The present invention relates to a signal amplification circuit, in particular, to a sense amplification circuit which is used for data read out of a semiconductor memory device.
2. Description of the Background Art
Conventionally, in a non-volatile semiconductor memory device, or the like, a signal amplification circuit is used which amplifies and senses the difference between currents which flow through two input nodes, respectively, so as to carry out data output in accordance with this current difference. In such a signal amplification circuit, detection sensitivity, detection precision, operational speed, power consumption, and the like, are regarded as important from the viewpoint of performance.
FIG. 14 is a circuit diagram showing the configuration of a signal amplification circuit which is used as a sense amplifier in a non-volatile semiconductor memory device according to a prior art.
Referring to FIG. 14, the signal amplification circuit 1 according to a prior art amplifies the difference between currents which flow through sense input nodes Ni1 and Ni2, respectively, so as to reflect that difference in the signal level of the output signal DOUT.
The sense input node Ni1 is electrically connected to a memory cell transistor MCT via a selection gate YG and a bit line BL at the time of data read out. The memory cell transistor MCT has a control gate which is connected to a word line WL and the source and drain thereof are connected to the ground voltage Vss and the bit line BL, respectively.
The threshold voltage of the memory cell transistor MCT changes in accordance with the level of the stored data (hereinafter referred to as xe2x80x9cstored data levelxe2x80x9d). Accordingly, by activating the word line WL to a predetermined voltage, the threshold voltage of the memory cell transistor MCT, that is to say, a current in accordance with the stored data level, can be made to flow through the memory cell transistor MCT. In general, a plurality of memory cell transistors MCT are selected in response to the activation of one word line WL and a current is made to flow, in accordance with the stored data level, through the plurality of corresponding bit lines, respectively.
The selection gate YG turns on in response to the activation of the column selection line YL. Through a selective activation of the column selection line YL in accordance with the column selection result, one of the plurality of memory cell transistors MCT, which have been selected in response to the. activation of the word line WL, is further selected and is connected to the sense input node Ni1.
In this manner, in response to the selective activation of the word line WL and the column selection line YL, the selected memory cell transistor MCT is electrically connected to the sense input node Ni1.
On the other hand, the sense input node Ni2 is electrically connected, at the time of data read out, to the reference memory cell transistor MCRT for giving the reference value at the time of data read out. The reference memory cell transistor MCRT has a fixed threshold voltage which becomes the reference.
In the same manner, as in the configuration of the memory cell transistor MCT, a word line WRL, a selection gate YGR, a bit line RBL and a column selection line YRL are arranged in the reference memory cell transistor MCRT. The word line WRL and the column selection line YRL are activated at the time of data read out.
The signal amplification circuit 1 amplifies the difference between currents which are, respectively, made to flow through the sense input nodes Ni1 and Ni2 so as to set the signal level of the output signal DOUT.
The signal amplification circuit 1 has an N channel type field effect transistor Ta, a P channel type field effect transistors Tb and Tc which form a current mirror, a diode DC for carrying out a current-voltage conversion and a bias circuit 2. Hereinafter, in the present specification, N channel type field effect transistors and P channel type field effect transistors are also referred to simply as N type transistors and P type transistors.
In response to an enabling signal /EN1 which is inputted to the bias circuit 2, the N type transistor Ta turns on so that the sense input node Ni1 and the gates of the P type transistors Tb and Tc which form the current mirror are electrically connected.
In response to the turning on of the N type transistor Ta, a memory cell current Icell, which corresponds to the stored data level of the selected memory cell transistor MCT, is made to flow through the current path including power supply voltage Vcc, P type transistor Tb, N type transistor Ta, sense input node Ni1, selected memory cell transistor MCT, and ground voltage Vss.
The voltage level of the sense input node Ni1 is maintained, at least, at the threshold voltage of the N type transistor Td, or more, within the bias circuit 2 by means of the effect of the bias circuit 2 The P type transistor Tc which forms the current mirror with the P type transistor Tb allows the inside current Ic in accordance with the memory cell current Icell to flow through the node Nc. The ratio of the memory cell current Icell to the inside current Ic is determined by the ratio of the current driving performance of the P type transistors Tb and Tc, that is to say, the ratio of the transistor size.
The diode DC is formed of an N type transistor which is connected so as to form a diode and generates a voltage, at the node Nc, in accordance with the inside current Ic, which flows through the node Nc.
The signal amplification circuit 1 further includes a bias circuit 3, an N type transistor Te, P type transistors Tf and Tg which form a current mirror and a diode DR.
In response to an enabling signal /EN2 which is inputted to the bias circuit 3, the sense input node Ni2 and the gates of the transistors Tf and Tg which form the current mirror are electrically connected.
In response to the turning on of the N type transistor Te, the reference current Iref, which corresponds to the reference memory cell transistor MCRT, flows through the sense input node Ni2.
The bias circuit 3 operates in the same manner as the bias circuit 2 and maintains the voltage level of the sense input node Ni2 at least at the threshold voltage of the transistor Th, or more.
The same configuration as in the memory cell current Icell is provided for the reference current Iref which flows through the reference memory cell transistor MCRT and the P type transistor Tg which forms the current mirror with the P type transistor Tf allows the inside current Ir in accordance with the reference current Iref to flow through the node Nr. The ratio of the reference current Iref to the inside current Ir is determined by the ratio of the current driving performance of the P type transistors Tf and Tg, that is to say, the ratio of the transistor size.
The diode DR is formed of an N type transistor which is connected so as to form a diode in the same manner as in the diode DC and generates a voltage in accordance with the reference current Iref at the node Nr.
The signal amplification circuit 1 further includes a differential amplifier 4.
The differential amplifier 4 amplifies the voltage difference between the nodes Nc and Nr and sets the signal level of the output signal DOUT within the range between the power supply voltage Vcc and the ground voltage Vss. The configuration of the differential amplifier 4 is generic, of which the detailed description is omitted.
In such a configuration, a memory cell current Icell which flows through the selected memory cell transistor MCT is compared with the reference current Iref which flows through the reference memory cell transistor MCRT so that the output signal DOUT in accordance with the stored data level of the memory cell transistor MCT can be outputted. Accordingly, data read out of a non-volatile semiconductor memory device is possible by using such a signal amplification circuit 1.
In the signal amplification circuit 1 according to the prior art, however, respective currents which are inputted into the sense input nodes Ni1 and Ni2 are once converted to voltages so that data read out is carried out through the comparison between these converted voltages.
In general, the above described voltage difference in the case of the usage for the data read out of a non-volatile semiconductor device, that is to say, the voltage difference between the nodes Nc and Nr in FIG. 14 becomes a comparatively microscopic value. Thereby, it becomes necessary to carry out a voltage amplification by providing a differential amplifier 4.
In addition, in recent years, a multi level cell, or the like, which stores not only one bit information showing either xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d but also information of a plurality of bits in one memory cell has been developed and in this case a current difference to be sensed can be set at a further smaller value.
Though in this case, it becomes necessary to secure a gain in the data read out by increasing the number of stages of differential amplifiers, or the like, the increase of the number of stages of the differential amplifiers causes the problems such as a delay of the operational speed or an increase of the current consumption.
In order to solve such problems, a configuration of a sense amplifier is disclosed, for example, in FIG. 1 of the gazette of Japanese Patent Laying-Open No. 6-180988(1994), where a voltage in accordance with the comparison result of currents inputted to the sense input nodes is directly generated so as to carry out the data output based on this voltage.
In the sense amplifier disclosed in the above gazette, however, the voltage generated through the comparison of the input currents is received by a mere inverter at the final stage so as to carry out the data output. Therefore, there is a possibility that it will become difficult to maintain the corresponding relationships, between the comparison result of the input currents and the outputted data level, at a constant level while removing the influence of a disturbance.
For example, a fluctuation of the operational power supply voltage. can be cited as a representative example of such a disturbance. That is to say, the threshold value of the inverter at the final stage, that is to say, an input voltage level to the above inverter, which corresponds to the switching point of the output level of said inverter, is necessary to be set to correspond to the condition where the input currents are equal and, on the other hand, the threshold value of the inverter fluctuates by receiving the influence of the operational power supply voltage. As a result of this, the output from the above inverter cannot precisely reflect the comparison result between the currents which are the detection objectives and there is a possibility that the precision of the data read out will deteriorate.
In particular, in recent years, a lower voltage operation has been achieved, from the viewpoint of lower power consumption, of a semiconductor device and there is the concern that the fluctuation of the operational power supply voltage has a great impact on the precision of the data read out.
The purpose of this invention is to provide a signal amplification circuit, for amplifying and sensing the difference between input currents which can prevent the deterioration of data read out due to disturbance, and to provide a semiconductor memory device including the same.
This invention concisely described is a signal amplification circuit for amplifying and sensing the difference between the input current and the reference current which flow through the first and the second input nodes, respectively, which includes a reference voltage generation part, a first transistor, a current comparison part and an output level setting part. The reference voltage generation part generates a reference voltage at a first node in accordance with the reference current. The first transistor is of a first conductive type and is electrically connected between a first power supply node, which supplies a first voltage, and the first input node so as to allow the input current to pass through it. The current comparison part generates a voltage in accordance with the difference between the input current and the reference current at a second node based on the reference voltage. The current comparison part includes a second transistor of the. first conductive type and a third transistor of a second conductive type, which is an opposite conductive type to the first conductive type. The second transistor is electrically connected between the first power supply node and the second node and forms a current mirror with the first transistor. The third transistor has a control electrode which receives the input of the reference voltage and is electrically connected between a second power supply node to which the second voltage is supplied, and the second node. The output level setting part outputs a voltage in accordance with a sensing result at the output node in accordance with the voltage of the second node. The output level setting part includes a fourth transistor of the first conductive type, which is electrically connected between the first power supply node and the output node and which has a control electrode that receives a voltage in accordance with the reference voltage as well as a fifth transistor of the second conductive type, which is electrically connected between the output node and the second power supply node and has a control electrode which is connected to the second node. Under the condition where the input current and the reference current are equal, currents which flow through the fourth and the fifth transistors, respectively, are in balance.
Accordingly, the main advantage of this invention is that the voltage dependency with the first or the second power supply node is reduced so that the threshold of the data read out can be set in a stable manner to correspond to the condition where the reference current and the input current are imbalance. As a result, the occurrence of detection error due to the fluctuation of the power supply voltage can be prevented.
According to another aspect of this invention, a semiconductor memory device including a plurality of memory cells, a reference memory cell, a selection part and a sense amplification circuit are provided. A current amount in accordance with the level of the stored data is made to flow through one of a plurality of memory cells at the time of data read out. A current amount which becomes the reference of the data read out is made to flow through the reference memory cell. The selection part electrically connects one of the plurality of the memory cells which has been selected as the objective of the data read out as well as the reference memory cell to the first and the second sense input nodes, respectively, in the data read out. The sense amplification circuit amplifies and senses the difference between the input current and the reference current which respectively flows through a first and second sense input nodes. The sense amplification circuit includes a reference voltage generation part for generating a reference voltage at a first node in accordance with the reference current, a first transistor of a first conductive type which is electrically connected between a first power supply node that supplies a first voltage and a first input node so as to allow the input current to pass through and a current comparison part for generating a voltage in accordance with the difference between the input current and the reference current at a second node. The current comparison part has a second transistor of the first conductive type that is electrically connected between the first power supply node and the second node and forms a current mirror with the first transistor as well as a third transistor, of a second conductive type that is the opposite conductive type of the first conductive type, that has a control electrode which receives an input of the reference voltage and is electrically connected between a second power supply node which supplies a second voltage and a second node. The sense amplification circuit further includes an output level setting part for outputting the read out data which has a voltage in accordance with a sensing result to the output node in accordance with the voltage of the second node. The output level setting apart has a fourth transistor of the first conductive type, which is electrically connected between the first power node and the output node and which has a control electrode which receives an input of the voltage in accordance with the reference voltage as well as a fifth transistor of the second conductive type, which is electrically connected between the output node and the second power supply node and which has a control electrode connected to the second node. Under the condition where the input current and the reference current are equal, currents which respectively flow through the fourth and the fifth transistors are in balance.
Accordingly, a semiconductor memory device can be provided which includes, as a sense amplification circuit, a signal amplification circuit which allows the threshold of the data read out to be stably set by corresponding to the condition where the reference current and the input current are in balance while removing the voltage dependability of the first or the second power supply node. Accordingly the precision of the data read out due to the fluctuation of the power supply voltage can be prevented from deteriorating.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.